The present invention relates generally to chip stacks, and more particularly to a 3-D chip stack with a post in ring interconnect.
As is currently known in the art, packaged components are often stacked using a variety of approaches. In all of the approaches to date, the concept has been for the end user to mount the stacks on the surface of a solid board such as a printed circuit board (PCB). More particularly, one of the most commonly used techniques to increase memory capacity is the stacking of memory devices into a vertical chip stack, sometimes referred to as 3D packaging or Z-Stacking. In the Z-Stacking process, from two to as many as eight memory devices or other integrated circuit (IC) chips are interconnected in a single component (i.e., a chip stack) which is mountable to the xe2x80x9cfootprintxe2x80x9d typically used for a single packaged device such as a packaged chip. The Z-Stacking process has been found to be volumetrically efficient, with packaged chips in TSOP (thin small outline package) or LCC (leadless chip carrier) form generally being considered to be the easiest to use in relation thereto. Though bare dies may also be used in the Z-Stacking process, such use tends to make the stacking process more complex and not well suited to automation.
In the 3-D stacking process, a solder bridge is typically applied to interconnect neighboring layers or PCB substrates that carry IC devices. However, in the ever changing world of electronics, smaller, faster, and more functionality are always requested. Shrinkage of devices generally results in more I/O""s in a smaller package. Design rules are requiring shorter signal paths to accommodate the faster die speeds. With the tighter pitches becoming more prominent in the packages, solder bridging between neighboring interconnects becomes more difficult to control. This forces the issue of eliminating solder paste because of its limitation on density. Another concern relates to environmental issues with the lead content in solder and the disposal thereof. A method to resolve these problems is required.
The invention provides a post in ring interconnection to replace the solder joints between neighboring substrates or layers for stacking IC devices, such that the limitation in density and environmental problems caused by lead content attendant to the use of solder paste are eliminated.
A first PCB substrate is provided with conductive pads on two opposing surfaces thereof. The two conductive pads are electrically connected to each other by a via through the PCB substrate. A retaining ring is plated on a peripheral portion of one of the conductive pads of the first PCB substrate, so that a pocket or recess is formed within the retaining ring. A second PCB substrate is provided, again, with two conductive pads on two opposing surfaces thereof. A post is disposed on a center portion of one of the conductive pads of the second PCB substrate. When the first PCB substrate is stacked with the second PCB substrate, the conductive pad with the retaining ring is aligned with the conductive pad with the post. In addition, a conductive paste or ink is applied into the pocket. In this way, the post is received in the pocket and connected to the conductive pad of the first PCB substrate. By a lamination process, a eutectic bond is formed of the conductive paste between the two adjoining pads of the two PCB substrates.
In addition, an adhesive is applied between the adjoining surfaces of the first and the second PCB substrates. Using a lased or drilled technique, the post is inserted into the adhesive and aligned on the conductive pad of the second PCB substrate. In the reflow process, the adhesive reflows to create a tight bond between the first and the second PCB substrates.